1. Field of the Invention
The invention relates to a memory cell array having a plurality of electrically-rewritable memory cells, and a semiconductor memory having such a memory cell array.
2. Description of the Related Art
A memory cell array having a plurality of electrically-rewritable memory cells is well-known. The conventional memory cell array includes a plurality of word lines, a plurality of bit lines, which are perpendicular to the word lines and a plurality of memory cells, each of which is disposed at one of the intersections between the word lines and the bit lines so that the memory cells are disposed in matrix. Each memory cell includes a transistor and a capacitor, and the operation of reading out from a memory cell and the operation of writing data in a memory cell are performed by charging or discharging a capacitor. In case of a flash memory, each memory cell includes a transistor having a floating gate for storing electric charges. Thus, the operation of reading out from a memory cell and the operation of writing data in a memory cell are performed by the existence of the electric charge at the floating gate. In either case, in order to readout information from a certain memory cell, the voltage is applied to the word line, which is connected to the memory cell so that the information stored in the memory cell is outputted to the bit line. According to the conventional memory cell array, the length of the route that the electric current flows in the bit line depends on the location of the memory cell being accessed (the location of the word line to which the voltage is applied). The longer the length of the bit line in which the electric current flows is, the higher the resistance value of the bit line is. Thus, at the end of the bit lines to which a sense amplifier is connected, the electric current value varies, depending on the location of the memory cell. To avoid the variation of the electric current value, an architecture of the memory cells such that the length of the route that the electric current flows in any bit line becomes the same is disclosed in the following Reference.
Reference: U.S. Pat. No. 6,633,496 B1
However, according to the architecture of the memory cell disclosed in the Reference, a single metal bit line is set at either a source electric potential of a memory cell being accessed or a drain electric potential of a memory cell being accessed. Compared with architecture of the memory cell in which a single metal bit line is set at one of the source and a drain electric potentials of a memory cell being accessed, the power consumption at the time of charging or discharging at the metal bit line becomes larger, and the time for charging or discharging at the metal bit line becomes longer.